Intel Clearwater Forest is a data center processor that Intel built on its 18A process node and launched at Computex 2026 to target agentic AI orchestration workloads. Intel confirmed the flagship Xeon 6990E+ SKU runs up to 288 cores at 450W TDP, with the full Clearwater lineup spanning 144 to 288 cores at TDPs from 330W to 450W, placing core count ahead of NVIDIA's Vera CPU and Arm's recently announced AGI CPU by 200 or more cores per socket.
The architecture stacks twelve compute tiles on the 18A node atop three Intel 3 tiles housing memory controllers and L3 cache. PCIe, CXL connectivity, and 16 dedicated accelerators are handled by a pair of I/O dies borrowed from the Xeon 6900P series, meaning Clearwater drops into existing board designs without an OEM platform ramp. Memory support reaches 12 channels of DDR5 at 8,000 MT/s per socket. Intel says that yields roughly 750 GB/s of socket bandwidth, working out to between 2.5 and 5 GB/s per core depending on SKU selected.
The cores are Darkmont E-cores, a stripped-down design trading AVX-512, AMX matrix acceleration, and Hyperthreading for denser packing. Intel's case for the tradeoff: agentic harnesses spend most compute time on HTTP requests, Python execution, SQL queries, and API calls, none of which require wide vector registers. Clearwater's E-cores deliver 17% higher instructions-per-clock over the previous E-core Xeon generation at faster boost clocks; the 16 on-die accelerators cover cryptography, compression, decompression, and load balancing.
Intel's consolidation pitch is that one Clearwater Forest system can replace up to nine second-generation Xeon Scalable boxes. That argument faces a headwind: memory prices have more than tripled since early 2025, making 12-channel DDR5 a meaningful cost item at scale. Service providers weighing whether to sweat existing servers a bit longer have a legitimate case against upgrading early.
AMD's roadmap creates the more pressing deadline. AMD is widely expected to announce Venice Epycs with high core counts in July, using compact Zen-architecture cores that preserve AVX-512 at high density. That would narrow the core-count lead Clearwater holds today while retaining the vector features Intel's chip gave up. For operators placing server orders now, the practical question is whether agentic workload pressure justifies committing to Clearwater before Venice pricing and availability are known.
