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Marvell Structera X Second Generation Adds Six Memory Channels and Four-Host Sharing

Marvell's Structera X 3406 and 3506 CXL 3.2 memory expanders add six DDR channels and four-host sharing for AI servers, sampling in Q1 2027.

Marvell Structera X 3506 chip with a silver heat spreader on a blue package substrate, on a white background
Structera X 3506 · Credit: Marvell

Marvell's second-generation Structera X controllers push CXL memory expansion to six DDR channels per chip, 50% more than the first generation, for AI servers whose inference jobs run short of memory long before they run short of compute.

The Structera X 3406 and 3506 are CXL 3.2 expanders on show at the OCP Global Summit in San Jose. Per Marvell, the 3406 drives 18 DDR4 RDIMM slots for 9TB per controller, and the 3506 drives 12 DDR5 slots for 6TB, both on PCIe Gen 6. Inline LZ4 compression, with five times the throughput of the prior generation, stretches effective capacity up to 2 to 3 times depending on workload. Up to four hosts can share the pool.

Samples are expected in Q1 2027, and Marvell gave no pricing for either part. The first-generation Structera X 2404 and 2504, which share the architecture, already ship to hyperscalers. The Structera X release adds error correction against DRAM device failures and a post-quantum security stack. Marvell calls the six-channel design, the four-host sharing and the post-quantum security industry firsts, which are its claims rather than verified rankings.

The performance numbers come from Marvell's comparison against its own first generation. For LLM serving, it cites up to 40% to 50% faster time to first token at the same context length, or context windows up to twice as long at the same latency. For deep learning recommendation models, it cites up to twice the queries per second. Marvell did not describe the test systems or models behind those figures, and no independent results exist yet.

The more telling detail for buyers is the DDR4 support on the 3406. Jim Handy of Objective Analysis, quoted by Marvell, says the current memory shortage is pushing IT managers to move used DDR4 modules into DDR5 systems through CXL for immediate savings. A controller that adds capacity through compression and sharing, instead of newly bought DIMMs, fits that logic. Supporting statements came from AMD, Arm, Alibaba, Meta, Samsung and SK hynix, though the release carries no named customer deployment of the new parts. Sampling is the stage where partners receive test silicon, so servers built on the 3406 and 3506 reach production well after that.

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Hannah Vogel

Hannah Vogel covers consumer devices, wearables, storage, and the displays and peripherals on every desk for techshooked. She tests skeptically: run the device under real conditions, report the failure cases reviews tend to omit, and never call a product good on first impressions alone.